The memory cells in a semiconductor static random access memory (RAM) array typically require 6 transistors (6T). Four of these transistors are coupled as a cross-coupled latch and provide storage of a logical "1" or "0." The two additional transistors are used as pass transistors, to couple the memory cell to complementary bit lines. To write a bit to a memory cell location, a word line for the cell is selected, which turns on the pass transistors. The complementary bit lines are then charged to opposite states by a writer-driver circuit, causing the memory cell to store the selected bit. The bit stored in the memory cell may be read by a sense amplifier that measures the difference in voltage between the two bit lines. Reversing the voltages on the bit lines forces the transistors to change states and store the alternate bit. Although it is understood that such semiconductor static RAM arrays may be used with any kind of transistor, metal-oxide semiconductor (MOS) transistors will be used herein for exemplary purposes.
Five transistor (5T) MOS static RAM cells have been previously developed that use a single bit line instead of a pair of complementary bit lines and thus only require a single pass transistor. It is more difficult to write a logic 1 to a 5T MOS static RAM cell that is storing a logic 0 as compared to a 6T MOS static RAM cell that is storing a logic 0, because the process of writing a logic 1 to the 5T cell includes applying a logical high voltage to a node that is initially nearly at ground voltage. Thus, it is difficult to raise this node voltage high enough to cause the non-conducting transistors in the cell to change state so that the logical 1 may be written to the cell.
Several methods have been recommended to overcome this problem with 5T MOS static RAM cells, but these methods involve the use of alternate voltage levels for bit lines and word lines that are difficult to implement in practice. These methods are also difficult to implement in a low voltage and low power application, and are impractical for an application specific integrated circuit (ASIC) design.